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MCP servers tagged fpga
19 live MCP servers tagged "fpga", ranked by trust score. Tags come from package metadata and repository topics, so this list covers servers across every category that work with fpga.
Vivado MCP
Vivado MCP server — 让 Claude Code / Cursor / Codex 驱动本地 FPGA 全流程。30 个精选工具、8 个证据驱动 Prompt、doctor 环境自检、GUI/Tcl/attach 会话，以及时序和 CRITICAL WARNING 中文诊断。
Vivado MCP
Vivado MCP server — 让 Claude Code / Cursor / Codex 驱动本地 FPGA 全流程。30 个精选工具、8 个证据驱动 Prompt、doctor 环境自检、GUI/Tcl/attach 会话，以及时序和 CRITICAL WARNING 中文诊断。
MCP
TypeScript HDL - design, simulate, and synthesize digital circuits with a unified toolchain.
Silica Eda
AI-native EDA environment: an MCP server that lets AI agents simulate, synthesize, lint, formally verify and place-and-route RTL
SynthPilot
Talk to your AI. Watch it drive Vivado. — an MCP server for AI-driven FPGA development on Xilinx Vivado.
Routeagents Fpl26
LLM-guided agent for post-route FPGA timing optimization: a measured playbook over Vivado and RapidWright via MCP (FPL'26 Agentic FPGA Backend Optimization Contest, top-5)
CPLD FPGA Toolkit
AI agent skills + MegaMemory knowledge graph for CPLD (WinCUPL/CUPL) and FPGA (iCEstudio/Verilog) design — describe in natural language, get validated, compiled hardware
catallo/misterclaw
discovers 70+ systems with dynamic core/ROM scanning.
Oh My Fpga
Don't memorize 500 tools — describe the chip outcome you want. Open FPGA skill pack (timing closure, CDC audit, full flow, Zynq bring-up…) for the SynthPilot MCP.
Gowin MCP
BETA — MCP server that turns Gowin EDA build reports into structured data: resource usage, fMax per clock, timing violations, and build-to-build comparison. Sipeed Tang / GW1N / G…
Ece Tool Suite
Desktop app for bench instrument control over SCPI/VISA (oscilloscope, multimeter, spectrum analyzer, power supply) with SPICE-verified power supply design, RTL/FPGA tooling, part…
Weft MCP
MCP Server for Quartus 25.1
FpgaZeroMCP
An open-source Model Context Protocol server that gives AI assistants a complete FPGA toolchain — lint, simulate, synthesize, place-and-route, and a live IP core registry backed b…
Hw Sw Bridge
Peer-to-peer MCP server for two Claude Code agents to coordinate over an encrypted Tailscale tunnel. Built for Computer Architecture final project — HW agent (Windows/Vivado) and…
Neorv32 MCP
AI agent bridge for NeoRV32 hardware: 15 MCP tools (UART + JTAG) for safe FPGA debug. Works with OWUI, VS Code, Cursor.
Adr Fpga Bootstrap
Portable Ubuntu 22.04 Podman bootstrap for AMD Vivado/Vitis 2024.1, RFSoC, external licensing, and Vivado MCP
Shuttle Stack
Local-inference layer for coding agents: your files are read by llama.cpp on your machine, not by your agent's context. MCP, rootless Podman, no egress, cited answers, measured.
Verilog Builder Pluggin
⚡ Prompt-driven FPGA & RTL workflow for AI assistants: create, build, fix, simulate Verilog via MCP. Vivado + Icarus Verilog. Claude Code, Codex, Hermes, OpenClaw.
Vivado MCP
Vivado MCP server — 让 Claude Code / Cursor / Codex 驱动本地 FPGA 全流程。30 个精选工具、8 个证据驱动 Prompt、doctor 环境自检、GUI/Tcl/attach 会话，以及时序和 CRITICAL WARNING 中文诊断。