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MCP servers tagged verilog
17 live MCP servers tagged "verilog", ranked by trust score. Tags come from package metadata and repository topics, so this list covers servers across every category that work with verilog.
Vivado MCP
Vivado MCP server — 让 Claude Code / Cursor / Codex 驱动本地 FPGA 全流程。30 个精选工具、8 个证据驱动 Prompt、doctor 环境自检、GUI/Tcl/attach 会话，以及时序和 CRITICAL WARNING 中文诊断。
Vibe Ic
AI-native IC design plugin with MCP-EDA — from natural-language intent to verified silicon.
SynthPilot
Talk to your AI. Watch it drive Vivado. — an MCP server for AI-driven FPGA development on Xilinx Vivado.
Verilog
Model Context Protocol (MCP) server for Verilog and SystemVerilog development
Verilog MCP Server
AI-powered Verilog/SystemVerilog MCP Server for Claude Code: generate testbenches, lint RTL code, and scaffold UVM verification environments
Cocotb
Model Context Protocol server for Python-based Cocotb co-simulation testbenches
CPLD FPGA Toolkit
AI agent skills + MegaMemory knowledge graph for CPLD (WinCUPL/CUPL) and FPGA (iCEstudio/Verilog) design — describe in natural language, get validated, compiled hardware
Agentic Asic
Autonomous Silicon Compilation & Signoff Orchestrator powered by EDA MCP Servers
Oh My Fpga
Don't memorize 500 tools — describe the chip outcome you want. Open FPGA skill pack (timing closure, CDC audit, full flow, Zynq bring-up…) for the SynthPilot MCP.
Gowin MCP
BETA — MCP server that turns Gowin EDA build reports into structured data: resource usage, fMax per clock, timing violations, and build-to-build comparison. Sipeed Tang / GW1N / G…
Ece Tool Suite
Desktop app for bench instrument control over SCPI/VISA (oscilloscope, multimeter, spectrum analyzer, power supply) with SPICE-verified power supply design, RTL/FPGA tooling, part…
Hw Verify MCP
MCP server giving AI agents a hardware constant-time, masking, and patch-completeness checker they cannot argue with
FpgaZeroMCP
An open-source Model Context Protocol server that gives AI assistants a complete FPGA toolchain — lint, simulate, synthesize, place-and-route, and a live IP core registry backed b…
Hw Agent Tooling
Landing page for AI agent tooling for hardware + ML systems (MCP, skills, EDA containers)
Rtl Review
Model Context Protocol server for AST-backed static RTL review, semantic bug detection, and code review scoring
Upf Insight
Deterministic power-intent intelligence for IEEE 1801 (UPF): validate, model, analyze and diff UPF before power-aware implementation. 77 rules, cross-file scope modeling, a CI qua…
Verilog Builder Pluggin
⚡ Prompt-driven FPGA & RTL workflow for AI assistants: create, build, fix, simulate Verilog via MCP. Vivado + Icarus Verilog. Claude Code, Codex, Hermes, OpenClaw.