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MCP servers tagged systemverilog
7 live MCP servers tagged "systemverilog", ranked by trust score. Tags come from package metadata and repository topics, so this list covers servers across every category that work with systemverilog.
Silica Eda
AI-native EDA environment: an MCP server that lets AI agents simulate, synthesize, lint, formally verify and place-and-route RTL
Verilog
Model Context Protocol (MCP) server for Verilog and SystemVerilog development
Verilog MCP Server
AI-powered Verilog/SystemVerilog MCP Server for Claude Code: generate testbenches, lint RTL code, and scaffold UVM verification environments
Chipleap
Design the chip your model needs: open-source architecture exploration from an AI workload to verified hardware, an X-HEEP RISC-V SoC or AXI4 IP, checked down to a routed layout o…
Shuttle Stack
Local-inference layer for coding agents: your files are read by llama.cpp on your machine, not by your agent's context. MCP, rootless Podman, no egress, cited answers, measured.
Digital EDA MCP
Model Context Protocol (MCP) server connecting AI agents to remote Linux EDA clusters for digital IC design, SystemVerilog/UVM, and formal verification.
Verilog Builder Pluggin
⚡ Prompt-driven FPGA & RTL workflow for AI assistants: create, build, fix, simulate Verilog via MCP. Vivado + Icarus Verilog. Claude Code, Codex, Hermes, OpenClaw.